Half Adder

Introduction

Half adder is a combinational circuit that performs an arithmetic addition of two bits. Half adder takes two inputs and produces two outputs. Let x, y be the two inputs, and S ( sum ), C ( carry ) be the two outputs.

Why we need two outputs?

This is because if we add ‘1’ and ‘1’ then the result is a 2-bit number. Therefore, we need two bits to represent the sum. S ( sum ) is used to represent the least significant bit and C ( carry ) is used to represent the most significant bit.

  • 0 + 0 = 00
  • 0 + 1 = 01
  • 1 + 0 = 01
  • 1 + 1 = 10

Truth Table

truth table for half adder

From the truth table, we can directly write

\\*S = x\overline{y} + \overline{x}y \newline\\*C = xy

K-map

k map half adder

Implementation of Half-adder

Half adder using AND, OR, NOT gate

half adder using and or not gate

Half adder using XOR and AND gate

half adder xor gate

Half adder using NAND gate

The minimum number of NAND gates required to design a half-adder is 5.

half adder using nand gates

Half adder using NOR gate

The minimum number of NOR gates required to design a half-adder is 5.

half adder using nor gates

Half adder using 2×1 Multiplexer

We need two 2×1 multiplexers to implement a half-adder. One for sum bit and one for carry bit.

half adder using multiplexer
half adder using 2x1 MUX

Half adder using 2 to 4 Decoder

Note

The term “Half-Adder” stems from the fact that two half-adders can be used to implement a full-adder.

References

  1. Digital Logic and Computer Design By M. Morris Mano
  2. Adders

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